One embodiment of the present invention relates to a system and method for testing hierarchical memory architectures. More specifically, one embodiment of the present invention relates to a system and method for applying stress to memory cells in a hierarchical memory architecture in a parallel fashion.
Hierarchical memory architecture, for example SRAM modules, have become an integral part of modern VLSI systems. Such highly integrated, high performance components for VLSI systems require complex fabrication and manufacturing processes. These processes may experience unavoidable parameter faults, which may impose unwanted defects on the SRAM modules or the larger VLSI systems. In one embodiment, redundancy is built into the memory architecture, providing one-for-one replacement for failed parts or subsystems.
During fabrication and manufacturing, electrical tests may detect defects that cause circuit failures in the VLSI systems or their components including the SRAM modules. Such detected defective systems or components are either repaired or discarded.
However, a class of defects exist that do not cause an immediate electrical failure but more likely results in a field failure after the part has been packaged and shipped. Field failures are costly as well as damaging to the manufacture's reputation for reliability. Such defects are commonly referred to as “weak defects.”
As a result, during manufacturing, the systems, subsystems and their smaller components are tested to detect such weak defects. The systems, subsystems and components are subjected to a stress, accelerating an impending failure so that the parts, subsystems or components may either be repaired or discarded before packaging. Logic parts of a chip may be stressed by passing predetermined high voltage test vectors through the chip circuits, subjecting the circuits to a predetermined high voltage and temperature.
Stressing a large memory structure could potentially take an impractical amount of time to complete during a manufacturing process. For example, a 10 megabit memory has 10 million entries, each of which must be tested. Sequentially testing 10 million entries would result in an extremely long test time. Such long test times are expensive.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.